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- ;; Author - Rick Vander Kam
- ;; Copyright (c) 1992 - All rights reserved
- ;; Modification history
- ;; --------------------
- ;; 2/29/92/rvk - initial file created from /usr/lib/dsp/ugsrc/fir3.asm
- ;;
- ;;------------------------------ DOCUMENTATION ---------------------------
- ;; NAME
- ;; dcblock (UG macro) - "dc notch" filter section
- ;;
- ;; SYNOPSIS
- ;; dcblock pf,ic,sout,aout0,sinp,ainp0,so10,si10,bb00,bb10,aa10
- ;;
- ;; MACRO ARGUMENTS
- ;; pf = global label prefix (any text unique to invoking macro)
- ;; ic = instance count (s.t. pf\_dcblock_\ic\_ is globally unique)
- ;; sout = output vector memory space ('x' or 'y')
- ;; aout0 = initial output vector memory address
- ;; sinp = input vector memory space ('x' or 'y')
- ;; ainp0 = initial input vector memory address
- ;; bb00 = initial coefficient of undelayed input
- ;; bb10 = initial coefficient of once delayed input
- ;; aa10 = initial coefficient of once delayed output
- ;; so10 = initial once delayed output state variable
- ;; si10 = initial once delayed input state variable
- ;;
- ;; DSP MEMORY ARGUMENTS
- ;; Access Description Initialization
- ;; ------ ----------- --------------
- ;; x:(R_X)+ Current output address aout0
- ;; x:(R_X)+ Current input address ainp0
- ;; x:(R_X)+ aa1 coefficient aa10
- ;; x:(R_X)+ so1 state variable so10
- ;; y:(R_Y)+ bb0 coefficient bb00
- ;; y:(R_Y)+ bb1 coefficient bb10
- ;; y:(R_Y)+ si1 state variable si10
- ;;
- ;; DESCRIPTION
- ;; The dcblock unit-generator implements a one-pole,
- ;; one-zero filter section in direct form. For best performance,
- ;; output memory space should be y.
- ;;
- ;; In pseudo-C notation:
- ;;
- ;; ainp = x:(R_X)+;
- ;; aout = x:(R_X)+;
- ;; aa1 = x:(R_X)+;
- ;; so1 = x:(R_X)+;
- ;; bb0 = y:(R_Y)+;
- ;; bb1 = y:(R_Y)+;
- ;; si1 = y:(R_Y)+;
- ;;
- ;; for (n=0;n<I_NTICK;n++) {
- ;; in = sinp:ainp[n];
- ;; output = sout:aout[n] = bb0*in + bb1*si1 + aa1*so1;
- ;; si1 = in;
- ;; so1 = output;
- ;; }
- ;;
- ;; DSPWRAP ARGUMENT INFO
- ;; dcblock (prefix)pf,(instance)ic,(dspace)sout,(output)aout,
- ;; (dspace)sinp,(input)ainp,so1,si1,bb0,bb1,aa1
- ;;
- ;; MAXIMUM EXECUTION TIME
- ;; ???
- ;;
- ;; MINIMUM EXECUTION TIME
- ;; ???
- ;;
- ;; SOURCE
- ;; /user/rvk/ee265/test/dcblockUG/dcblock.asm
- ;;
- ;; SEE ALSO
- ;; /usr/lib/dsp/ugsrc/biquad.asm - two-pole, two-zero filter section
- ;; /usr/lib/dsp/ugsrc/onepole.asm - one-pole filter section
- ;; /usr/lib/dsp/ugsrc/twopole.asm - two-pole filter section
- ;;
- ;; ALU REGISTER USE
- ;; X0 = y(n-1) = so1 = once delayed output
- ;; X1 = x(n), x(n-1) = in, si1 = undelayed and once-delayed input
- ;; Y0 = bb0,aa1 = undelayed and once-delayed output signal coefficients
- ;; Y1 = bb1 = once-delayed signal coefficient
- ;; A = multiply-add accumulator
- ;; B = holder for bb0
- ;;
- dcblock macro pf,ic,sout,aout0,sinp,ainp0,so10,si10,bb00,bb10,aa10
- new_xarg pf\_dcblock_\ic\_,aout,aout0 ; output address arg
- new_xarg pf\_dcblock_\ic\_,ainp,ainp0 ; input address arg
- new_xarg pf\_dcblock_\ic\_,aa1,aa10 ; once delayed output coeff
- new_xarg pf\_dcblock_\ic\_,si1,si10 ; once delayed input sample
- new_yarg pf\_dcblock_\ic\_,bb0,bb00 ; undelayed input coeff
- new_yarg pf\_dcblock_\ic\_,bb1,bb10 ; once-delayed input coeff
- new_yarg pf\_dcblock_\ic\_,so1,so10 ; once-delayed output
-
- move x:(R_X)+,R_O ; output address to R_O
- move x:(R_X)+,R_I1 ; input address to R_I1
-
- move x:(R_X)+,Y0 ;aa1 to Y0
- move x:(R_X),X1 y:(R_Y)+,B ; si1 to X1, bb0 to B
- move y:(R_Y)+,Y1 ; bb1 to Y1
- move y:(R_Y),X0 ; so1 to X0
- mpy X1,Y1,A ; A = si1*bb1
- macr X0,Y0,A sinp:(R_I1)+,X1 ; A += so1*aa1, update si1=x(n)
- tfr Y0,B B,Y0 ;bb0 to Y0, aa1 to B (swap)
- macr X1,Y0,A ;A += bb0*x(n) (= first output)
- do #I_NTICK-1,pf\_dcblock_\ic\_tickloop
- if "sout"=='y'
- move A,X0 A,sout:(R_O)+
- else
- move A,X0 ;update so1
- move A,sout:(R_O)+ ;ship output
- endif
- tfr Y0,B B,Y0 ;bb0 to B, aa1 to Y0
- mpy X1,Y1,A ;A=bb1*x(n-1)
- macr X0,Y0,A sinp:(R_I1)+,X1 ;A+=aa1*y(n-1), si1=x(n)
- tfr Y0,B B,Y0 ;bb0 to Y0, aa1 to B (swap)
- macr X1,Y0,A ;A += bb0*x(n)
- pf\_dcblock_\ic\_tickloop
- if "sout"=='y'
- move X1,x:(R_X)+ A,sout:(R_O)+
- move A,y:(R_Y)+
- else
- move A,sout:(R_O)+ ; ship last output
- move X1,x:(R_X)+ ; save si2 in mem arg
- move A,y:(R_Y)+ ; save so1 in mem arg
- endif
- endm
-
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